MCST-R1000
 MCST R1000 FPGA prototype | |
| General information | |
|---|---|
| Launched | 2010[1] |
| Designed by | MCST |
| Common manufacturer | |
| Performance | |
| Max. CPU clock rate | 750 MHz to 1 GHz |
| FSB speeds | 2 Gbps |
| Cache | |
| L1 cache | 48 KB |
| L2 cache | 2 MB |
| Architecture and classification | |
| Application | Embedded |
| Technology node | 100 mm² |
| Instruction set | SPARC V9 |
| Physical specifications | |
| Cores |
|
| Package | |
| History | |
| Predecessor | MCST-R500S |
| Successor | MCST-R2000 |
The MCST R1000 (Russian: МЦСТ R1000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.[2]
During development this microprocessor was designated as MCST-4R.[1]
MCST R1000 Highlights
[edit]- implements the SPARC V9 instruction set architecture (ISA)
- quad-core
- core specifications:
- in-order, dual-issue superscalar
- 7-stage integer pipeline
- 9-stage floating-point pipeline
- VIS extensions 1 and 2
- Multiply–accumulate unit
- 16 KB L1 instruction cache (parity protection)
- 32 KB L1 data cache (parity protection)
- size 7.6 mm2
- shared 2MB L2 cache (ECC protection)
- integrated memory controller
- integrated ccNUMA controller
- 1 GHz clock rate
- 90 nm process
- die size 128 mm2
- ~150 million transistors
- power consumption 15W
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References
[edit]- ^ a b "Участие ЗАО «МЦСТ» и ОАО «ИНЭУМ им.И.С.Брука» в международной выставке "ChipExpo – 2011" (итоги участия)", Новости (in Russian), MCST, archived from the original on 2011-05-11, retrieved 2011-12-06
- ^ Система на кристалле "МЦСТ-4R" (in Russian), MCST, retrieved 2011-11-18